The present invention relates generally to embedded central processing unit (CPU) systems and more particularly to a such a system which is upgradeable.
Embedded central processing unit (CPU) systems are utilized in a variety of applications. For example, a set top box controller is utilized with a television or the like to provide certain functionality and performance to that television. Typically, a set top box includes a set top box controller which utilizes an embedded processor for providing initialization and control and application code execution. Choosing the correct level of processor performance for a set top box controller is a difficult task due to the varying needs of users and applications. It is important that as much of the logic should be integrated to reduce the product cost to the smallest quantity of chips, and the smallest silicon dies for those chips. However, by putting limits on the core performance available on a set top box, limits are placed on the number of applications which can run on the set top box.
Accordingly, what is desired is a wide range of processor performance solutions from a low end microprocessor using only minimal set up and control to a high end microprocessor implementing a highly interactive set top box. For example, the highly interactive set top box might include web browsing, Java processing, two dimensional (2D) and three dimensional (3D) graphics. Accordingly, while it is desirable to have a single chip implementation at lowest system cost, given the various customer needs, it is also desirable to have a set top box in which the CPU performance is such that it can be adjusted for those various user""s needs. In addition, some customers have invested much software development in different processors"" architectures.
Accordingly, it would be desirable to allow those different processor architectures to function with an integrated embedded CPU system, such as a set top box, to ensure a solution is available for customers with alternative CPU architectures. This secondary CPU or CPU alternative should have direct access to key on-chip resources of the embedded CPU system.
In a preferred embodiment this type of system would be implemented utilizing a multiprocessor architecture to allow for such upgrades.
To enable such a multiprocessor system to perform efficiently, the following requirements must be met:
(1) Low latency notification path between multiple processors
(2) Common memory space for all of the processors
(3) Minimize external memory fetches for instruction execution
(4) Direct access to key resources in the embedded processor by a stand alone CPU.
What is needed, therefore, is an embedded CPU system such as a set top box controller which includes a processor core that can be used in a complementary fashion with higher performing external stand alone processors with minimal glue logic. The stand-alone processor must also have a low latency direct access path to key resources in the embedded CPU system. The product should be cost effective, easy to implement, and adaptable to existing technologies. The present invention addresses such a need.
A system and method in accordance with the present invention provides for an embedded CPU system which is upgradeable through the use of an external CPU which can be utilized therewith. In a first aspect, the embedded CPU system includes a CPU and a plurality of devices which are accessible by the CPU, via a device control register bus. The embedded CPU system includes logic coupled to the device control register bus for allowing access to the devices within the embedded CPU system by an external CPU.
In a second aspect, a highly integrated set top box (HISTB) comprises an embedded CPU (EMCPU) subsystem; an MPEG subsystem; a memory subsystem; and a peripheral subsystem. The HISTB includes at least one bus for allowing communication between the EMCPU subsystem, the MPEG subsystem, the memory subsystem and the peripheral subsystem. A device control register (DCR) bus is provided for coupling the EMCPU subsystem, the MPEG subsystem, the memory subsystem. The HISTB also includes logic within the HISTB that allows an external CPU to access the MPEG subsystem and its control register space.
In a preferred embodiment the present invention provides a highly integrated set top box controller with a processor performance that services the low-end with the added advantage of additional performance with the EMCPU operating as an I/O assist processor to the EXCPU. When the EXCPU operates as the primary processor these two processors serve as a high end set top box controller. A system and method in accordance with the present invention can also preserve much of the software programming model when migrating from a low end processor set top box controller to a higher end solution. A system and method in accordance with the present invention also offers a choice of preserving much of the existing software investment by allowing different processor architectures to function as the EXCPU.